Liquid crystal display device

ABSTRACT

A liquid crystal display device ( 100 A) according to the present invention includes a pixel ( 10 ) including first and second subpixels ( 10   a,    10   b ) and a first CS bus line ( 24   a ), which is associated with the first subpixel. The first subpixel includes a liquid crystal capacitor ( 13   a ) and a first storage capacitor ( 22   a ). The second subpixel includes a liquid crystal capacitor ( 13   b ). A first CS signal voltage applied to the first storage capacitor ( 22   a ) through the first CS bus line ( 24   a ) is an oscillation voltage, of which one period is shorter than one vertical scanning period, and has first and second potentials that define a maximum amplitude and a third potential between the first and second potentials. When a gate signal voltage Vg supplied to the gate bus line ( 12 ) that has been high goes low, the first CS signal voltage Vcsa supplied to its associated first CS bus line ( 24   a ) is at the third potential.

TECHNICAL FIELD

The present invention relates to a liquid crystal display device and more particularly relates to a liquid crystal display device with a multi-pixel structure that exhibits a wide viewing angle characteristic.

BACKGROUND ART

An MVA (multi-domain vertical alignment) mode liquid crystal display device has a wider viewing angle characteristic than a TN mode liquid crystal display device, and therefore, is currently used extensively in various liquid crystal display devices including TV monitors (see Patent Documents Nos. 1 and 2).

In an MVA mode liquid crystal display device, a domain control structure (which is also called an “alignment control structure”) is provided for each of the two substrates thereof, which face each other with a vertical alignment liquid crystal layer interposed between them, so as to face the liquid crystal layer, thereby producing multiple liquid crystal domains in which directors have multiple different alignment directions (i.e., tilt directions). As such a domain control structure, either an opening (e.g., a slit) that has been cut through an electrode or a dielectric projection (e.g., a rib) that has been formed on an electrode to face the liquid crystal layer is used.

Typically, domain control structures, which run straight in two directions that intersect with each other at right angles, are arranged on each of the two substrates. And the domain control structures provided for one and the other of the two substrates are arranged so as to run alternately and parallel to each other when viewed perpendicularly to the substrates. As a result, when a voltage is applied to the liquid crystal layer of an arbitrary pixel, four domains, in which liquid crystal molecules tilt in four different directions (which will be sometimes referred to herein as “liquid crystal domain director directions”), are produced between those linear domain control means so that the tilt direction of the liquid crystal molecules in any one of those four domains defines an angle of 90 degrees with respect to that of the liquid crystal molecules in an adjacent domain thereof. In a typical arrangement, four liquid crystal domains, in which the liquid crystal domain directors define an azimuth angle of 45 degrees with respect to the polarization axes (i.e., transmission axes) of two polarizers that are arranged as crossed Nicols, are formed. If an azimuth angle of zero degrees is supposed to be defined by the polarization axis direction of the one of the two polarizers (e.g., the horizontal direction on the display screen) and if the counterclockwise direction is supposed to be the positive direction, then the directors in those four liquid crystal domains will have azimuth angles of 45, 135, 225 and 315 degrees, respectively.

In this description, the “pixel” refers to the smallest unit of display to be conducted by the liquid crystal display device. In the case of a color display device, the “pixel” refers to the smallest unit for representing each of its primary colors, and is sometimes called a “dot”. In a typical color display device, one color display pixel is formed by three pixels that represent the colors red, green and blue that are the three primary colors of light. And by controlling the luminances of those pixels, the color display device conducts a display operation in colors.

Thus, to reduce the viewing angle dependence of the γ characteristic of an MVA mode liquid crystal display device, the applicant of the present application lately disclosed, in Patent Document No. 3, a liquid crystal display device that can reduce the viewing angle dependence of the γ characteristic by dividing a single pixel into a number of subpixels with mutually different brightness values, and a method for driving such a device. In particular, such a device can reduce the viewing angle dependence of the γ characteristic that manifests itself as a phenomenon that the display luminances at low grayscales become higher than a predetermined luminance (i.e., the image on the screen looks generally whitish) in a normally black mode display operation. Such a display or drive mode will sometimes be referred to herein as “area-grayscale display”, “area-grayscale drive”, “multi-pixel display” or “multi-pixel drive”.

The entire disclosures of Patent Documents Nos. 1 to 3 are hereby incorporated by reference.

CITATION LIST Patent Literature

-   Patent Document No. 1: Japanese Laid-Open Patent Publication No.     11-242225 (corresponding to U.S. Pat. No. 6,724,452) -   Patent Document No. 2: Japanese Laid-Open Patent Publication No.     2000-155317 (corresponding to U.S. Pat. No. 6,879,364) -   Patent Document No. 3: Japanese Laid-Open Patent Publication No.     2004-62146 (corresponding to U.S. Pat. No. 6,958,791)

SUMMARY OF INVENTION Technical Problem

However, the present inventors discovered via experiments that when the multi-pixel drive disclosed in Patent Document No. 3 was carried out, parallel lines that were displayed in the row direction looked smeared. This is a problem.

According to the multi-pixel driving method disclosed in Patent Document No. 3, by applying mutually different storage capacitor counter voltages (which will be sometimes referred to herein as “CS signal voltages”) to two electrically independent storage capacitors that are provided for two subpixels, mutually different effective voltages can be applied to the respective liquid crystal layers of the two subpixels as will be described later with reference to FIGS. 6 to 9. Specifically, after a predetermined display signal voltage has been applied to two subpixel electrodes, their TFTs turn OFF, thereby electrically disconnecting the subpixel electrodes from their source bus line. After that, the storage capacitor counter voltages are changed in two different patterns (in terms of the magnitude, the direction and the sign of the variation) with respect to the two subpixels, thereby making the effective voltages applied to the respective liquid crystal layers of the two subpixels different from each other.

According to that multi-pixel driving method, the combination of the polarity of the display signal voltage and the direction of the variation in storage capacitor counter voltage determines which of the two effective voltages applied to the respective liquid crystal layers of the two subpixels becomes higher than the other. That is why if a one dot inversion drive operation is carried out to avoid flicker, then bright subpixels will be arranged in a zigzag pattern in the row direction in accordance with the arrangement of polarities of the display signal voltages applied to the respective liquid crystal layers of the pixels. As a result, when lines that run parallel in the row direction are displayed, those lines will look smeared.

In order to overcome such a problem, the present invention has been made and one of its objects is to provide a liquid crystal display device with a multi-pixel structure that can display such lines running parallel in the row direction properly even when driven by the one dot inversion driving method.

Solution to Problem

A liquid crystal display device according to the present invention includes: a plurality of pixels that are arranged in columns and rows to form a matrix pattern, each of the plurality of pixels including first and second subpixels, the first subpixel exhibiting a higher luminance than the second subpixel at least at a particular grayscale; a plurality of source bus lines, each of which is associated with one of the columns of pixels; a plurality of gate bus lines, each of which is associated with one of the rows of pixels; a plurality of TFTs, each of which is associated with one of the first and second subpixels that each said pixel has; and a plurality of first CS bus lines, each of which is associated with the first subpixel of one of the pixels. The first subpixel includes: a liquid crystal capacitor which is formed by a first subpixel electrode, a liquid crystal layer, and a counter electrode that faces the first subpixel electrode via the liquid crystal layer; and a first storage capacitor which is formed by a first storage capacitor electrode that is electrically connected to the first subpixel electrode, an insulating layer, and a first storage capacitor counter electrode that faces the first storage capacitor electrode via the insulating layer. The second subpixel includes a liquid crystal capacitor that is formed by a second subpixel electrode and a counter electrode that faces the second subpixel electrode via the liquid crystal layer. A first CS signal voltage that is applied to the first storage capacitor counter electrode through its associated first CS bus line is an oscillation voltage, of which one period is shorter than one vertical scanning period, and has at least three potentials including first and second potentials that define a maximum amplitude and a third potential between the first and second potentials. When a gate signal voltage that is supplied to the gate bus line associated with an arbitrary row of pixels and that has been high goes low, the first CS signal voltage supplied to its associated first CS bus line is at the third potential.

In one embodiment, the third potential is the average of the first and second potentials.

In one embodiment, the liquid crystal display device further includes a plurality of second CS bus lines, each of which is associated with the second subpixel of one of the pixels. The second subpixel includes a second storage capacitor which is formed by a second storage capacitor electrode that is electrically connected to the second subpixel electrode, an insulating layer, and a second storage capacitor counter electrode that faces the second storage capacitor electrode via the insulating layer. A second CS signal voltage applied to the second storage capacitor counter electrode through its associated second CS bus line is constant through one vertical scanning period.

In one embodiment, the second CS signal voltage is equal to a counter voltage applied to the counter voltage.

In one embodiment, the second subpixel has no storage capacitors.

In one embodiment, the first and second subpixels are arranged in the same pattern both in two pixels that are adjacent to each other in a row direction and in two pixels that are adjacent to each other in a column direction.

In one embodiment, each of the plurality of first CS bus lines is connected to one of N CS trunk lines that are electrically independent of each other.

Advantageous Effects of Invention

The present invention provides a liquid crystal display device with a multi-pixel structure that can display lines running parallel in the row direction properly even when driven by a one dot inversion driving method, for example.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 A schematic representation illustrating an exemplary pixel structure for a liquid crystal display device 100A as an embodiment of the present invention.

FIG. 2 (a) is a diagram illustrating an electrical equivalent circuit corresponding to the pixel structure of the liquid crystal display device 100A and (b) is a diagram illustrating an electrical equivalent circuit corresponding to the pixel structure of a liquid crystal display device 100B as another embodiment of the present invention.

FIG. 3 A diagram illustrating the respective waveforms of various voltages (signals) to drive the liquid crystal display device 100A as an embodiment of the present invention.

FIG. 4 A graph showing how the effective voltages V1 and V2 applied to the respective liquid crystal layers of subpixels change with the display signal voltage Vs in the liquid crystal display device 100A.

FIG. 5A A diagram schematically illustrating the display state of the liquid crystal display device 100A being driven by a one-dot inversion drive method.

FIG. 5B A diagram schematically illustrating the display state of the liquid crystal display device 100B being driven by the one-dot inversion drive method.

FIG. 6 (a) through (f) show the respective waveforms of various voltages to drive the liquid crystal display device of Patent Document No. 3.

FIG. 7 A graph showing the relation between the voltages applied to the respective liquid crystal layers of two subpixels in the liquid crystal display device of Patent Document No. 3.

FIG. 8 A diagram schematically illustrating the display state of the liquid crystal display device of Patent Document No. 3 being driven by the one-dot inversion drive method.

FIG. 9 (a) through (j) show the waveforms of various voltages (signals) to realize the display state shown in FIG. 8.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings. However, the present invention is in no way limited to the specific embodiments to be described below.

FIG. 1 schematically shows an electrical configuration for a liquid crystal display device 100A as an embodiment of the present invention. The liquid crystal display device 100A has a plurality of pixels that are arranged in columns and rows to form a matrix pattern. And FIG. 1 illustrates the structure of one of those pixels.

The pixel 10 is divided into two subpixels 10 a and 10 b. To these subpixels 10 a and 10 b, connected are their associated TFTs 16 a and 16 b and their associated storage capacitors (CS) 22 a and 22 b, respectively. The gate electrodes of the TFTs 16 a and 16 b are both connected to the same gate bus line (scan line) 12. And their source electrodes are connected to the same source bus line (signal line) 14. The storage capacitors 22 a and 22 b are connected to their associated CS bus lines (storage capacitor lines) 24 a and 24 b, respectively. The storage capacitor 22 a includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18 a, a storage capacitor counter electrode that is electrically connected to the CS bus line 24 a, and an insulating layer (not shown) arranged between the electrodes. The storage capacitor 22 b includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18 b, a storage capacitor counter electrode that is electrically connected to the CS bus line 24 b, and an insulating layer (not shown) arranged between the electrodes. The respective storage capacitor counter electrodes of the storage capacitors 22 a and 22 b are independent of each other and have such a structure as receiving mutually different storage capacitor counter voltages (CS signals voltages) from the CS bus lines 24 a and 24 b, respectively.

FIG. 2( a) schematically shows the equivalent circuit of one pixel of the liquid crystal display device 100A. In this electrical equivalent circuit, the liquid crystal capacitors of the respective subpixels 10 a and 10 b are identified by the reference numerals 13 a and 13 b, respectively. Each of these liquid crystal capacitors 13 a and 13 b includes a subpixel electrode 18 a, 18 b, a liquid crystal layer, and a counter electrode 17 (that is shared by the subpixel electrodes 10 a and 10 b). In the following description, when described as electrical components, the liquid crystal capacitors 13 a and 13 b will also be referred to herein as “liquid crystal capacitors Clca and Clcb” and the storage capacitors 22 a and 22 b will also be referred to herein as “storage capacitors Ccsa and Ccsb”.

In the subpixel 10 a, one electrode of the liquid crystal capacitor Clca and one electrode of the storage capacitor Ccsa are connected to the drain electrode of the TFT 16 a, which is provided to drive the subpixel 10 a. The other electrode of the liquid crystal capacitor Clca is connected to the counter electrode 17. And the other electrode of the storage capacitor Ccsa is connected to the CS bus line 24 a. In the subpixel 10 b, one electrode of the liquid crystal capacitor Clcb and one electrode of the storage capacitor Ccsb are connected to the drain electrode of the TFT 16 b, which is provided to drive the subpixel 10 b. The other electrode of the liquid crystal capacitor Clcb is connected to the counter electrode 17. And the other electrode of the storage capacitor Ccsb is connected to the CS bus line 24 b. The gate electrodes of the TFTs 16 a and 16 b are both connected to the gate bus line 12 and their source electrodes are both connected to the source bus line 14. As long as the same gate signal voltage and the same display signal voltage (source signal voltage) are applied to the TFTs 16 a and 16 b, the TFTs 16 a and 16 b do not always have to share the same gate bus line 12 and/or the same source bus line 14.

Patent Document No. 3 also discloses the same pixel structure as that of this liquid crystal display device 100A. However, according to the multi-pixel driving method adopted in Patent Document No. 3, both of the storage capacitor counter voltages (CS signal voltages) supplied to the CS bus lines 24 a and 24 b are oscillation voltages. In this description, the “oscillation voltage” will refer herein to a voltage, of which one oscillation period is shorter than one vertical scanning period, unless otherwise stated.

On the other hand, the liquid crystal display device 100A as an embodiment of the present invention is configured to apply, in combination, a display signal voltage that is supplied from an associated source bus line 14 and a storage capacitor counter voltage (first CS signal voltage) that is supplied as an oscillation voltage from the CS bus line 24 a to the liquid crystal layer of one subpixel (which is a bright subpixel that is supposed to be the subpixel 10 a in the following description), and to apply a display signal voltage to the liquid crystal layer of the other subpixel (i.e., subpixel 10 b) without applying any oscillation voltage thereto. That is to say, substantially only the display signal voltage is applied to the liquid crystal layer of the other subpixel (i.e., the subpixel 10 b). That is why the storage capacitor counter voltage (second CS signal voltage) Vcsb applied to the subpixel 10 b of the liquid crystal display device 100A is not an oscillation voltage but a DC voltage (see Vcsb shown in FIG. 3). In this description, the “DC voltage” refers herein to a voltage that remains direct current (i.e., has a constant potential) through one vertical scanning period. The DC voltage applied as Vcsb had better be equal to the counter voltage to be applied to the counter electrode. It should be noted that the magnitude of a voltage applied to the liquid crystal layer is represented by reference to the potential at the counter electrode.

In addition, in the liquid crystal display device as an embodiment of the present invention, there is no need to apply an oscillation voltage to the liquid crystal layer of the subpixel 10 b, and therefore, a configuration in which the subpixel 10 b to be a dark subpixel has no storage capacitor as in the liquid crystal display device 100B shown in FIG. 2( b) may also be adopted. By omitting the storage capacitor in this manner, the aperture ratio of each pixel can be increased. In known 2× and 4× liquid crystal display devices, one vertical scanning period is 1/60 seconds (i.e., its vertical scanning frequency is 60 Hz). On the other hand, in liquid crystal display devices, of which one vertical scanning period is 1/120 or 1/240 seconds, the voltage applied to the liquid crystal layer needs to be retained for just a short time, and therefore, the storage capacitor can be omitted.

In the liquid crystal display device 100A, 100B as an embodiment of the present invention, the CS signal voltage Vcsa applied to the storage capacitor counter electrode of the subpixel 10 a through the CS bus line 24 a is an oscillation voltage, of which one period is shorter than one vertical scanning period, and has at least three potentials including first and second potentials that define a maximum amplitude and a third potential between the first and second potentials as shown in FIG. 3. It would be beneficial that the third potential is the average of the first and second potentials as illustrated in FIG. 3. As also shown in FIG. 3, the first, second and third potentials had better be maintained for a certain period. Furthermore, when the gate signal voltage that is supplied to a gate bus line and that has been high goes low (i.e., when the TFT turns OFF), the CS signal voltage supplied to the associated CS bus line is set to be the third potential. As a result, the liquid crystal display device 100A, 100B according to the present invention can overcome the problem with the multi-pixel drive of Patent Document No. 3 while reducing the viewing angle dependence of the γ characteristic.

It should be noted that “one vertical scanning period” refers herein to a period between a point in time when one gate bus line (or scan line) is selected and a point in time when that gate bus line is selected next time. In a known liquid crystal display device that is not driven by 2× or 4× driving method, one vertical scanning period corresponds to one frame period of a video signal if the video signal is a non-interlaced drive signal but corresponds to one field period of a video signal if the video signal is an interlaced drive signal. For example, in the case of an NTSC signal, one vertical scanning period of the liquid crystal display device is 16.7 msec, which is the inverse number of the field frequency (60 Hz) of the NTSC signal. Since the liquid crystal display device is not supposed to be interlaced driven, signal voltages are written on every pixel in both of odd- and even-numbered fields. That is why the inverse number of the field frequency of the NTSC signal becomes one vertical scanning period. It should be noted that in one vertical scanning period, the interval between a point in time when one gate bus line is selected and a point in time when the next gate bus line is selected is called “one horizontal scanning period (1H)”.

Hereinafter, it will be described with reference to FIGS. 6 through 9 what is a problem with the multi-pixel driving method disclosed in Patent Document No. 3. The liquid crystal display device 100A as an embodiment of the present invention not only has the same pixel structure, but also operates on the same principle, as its counterpart disclosed in Patent Document No. 3. That is to say, the liquid crystal display device 100A also makes a bright subpixel by supplying a storage capacitor voltage as an oscillation voltage. That is why the principle of the multi-pixel driving method disclosed in Patent Document No. 3 will also be described. In the following description, a liquid crystal display device that has the same configuration as what is shown in FIGS. 1 and 2( a) and that is supposed to be driven with the voltages shown in portions (a) through (f) of FIG. 6 will be described as an example.

Portions (a) through (f) of FIG. 6 schematically show the timings to apply respective voltages to drive a liquid crystal display device that has the same pixel structure as the liquid crystal display device 100A. Specifically, portion (a) of FIG. 6 shows the voltage waveform Vs of the source bus line 14; portion (b) of FIG. 6 shows the voltage waveform Vcsa of the CS bus line 24 a; portion (c) of FIG. 6 shows the voltage waveform Vcsb of the CS bus line 24 b; portion (d) of FIG. 6 shows the voltage waveform Vg of the gate bus line 12; portion (e) of FIG. 6 shows the voltage waveform Vlca of the pixel electrode 18 a of the subpixel 10 a; and portion (f) of FIG. 6 shows the voltage waveform Vlcb of the pixel electrode 18 b of the subpixel 10 b. In FIG. 6, the dashed line indicates the voltage waveform COMMON (Vcom) of the counter electrode 17.

In the following description, the liquid crystal capacitors Clca and Clcb of the subpixels 10 a and 10 b are supposed to have the same electrostatic capacitance CLC (V). The value of CLC (V) depends on the effective voltages (V) applied to the liquid crystal layers of the respective subpixels 10 a and 10 b. Also, the storage capacitors 22 a and 22 b that are connected independently of each other to the liquid crystal capacitors of the respective subpixels 10 a and 10 b are identified by Ccsa and Ccsb, respectively, and supposed to have the same electrostatic capacitance CCS.

First, at a time T1, the gate signal voltage Vg rises from VgL (low) to VgH (high) to turn the TFTs 16 a and 16 b ON simultaneously. As a result, the display signal voltage Vs on the source bus line 14 is applied to the subpixel electrodes 18 a and 18 b of the subpixels 10 a and 10 b to charge the liquid crystal capacitors Clca and Clcb. In the same way, the storage capacitors Ccsa and Ccsb of the respective subpixels are also charged with the display signal voltage Vs on the source bus line 14.

Next, at a time T2, the voltage Vg on the gate bus line 12 falls from VgH to VgL to turn the TFTs 16 a and 16 b OFF simultaneously and electrically isolate all of the liquid crystal capacitors Clca and Clcb and the storage capacitors Ccsa and Ccsb from the source bus line 14. It should be noted that immediately after that, due to the feedthrough phenomenon caused by a parasitic capacitance of the TFTs 16 a and 16 b and other factors, the voltages Vlca and Vlcb applied to the respective subpixel electrodes decrease by approximately the same voltage Vd to:

Vlca=Vs−Vd

Vlcb=Vs−Vd

respectively. Also, in this case, the voltages Vcsa and Vcsb on the CS bus lines are:

Vcsa=Vcom−Vad

Vcsb=Vcom+Vad

respectively.

Next, at a time T3, the voltage Vcsa on the CS bus line 24 a connected to the storage capacitor Ccsa rises from Vcom−Vad to Vcom+Vad and the voltage Vcsb on the CS bus line 24 b connected to the storage capacitor Ccsb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad. As the voltages on the CS bus lines 24 a and 24 b change in this manner, the voltages Vlca and Vlcb applied to the respective subpixel electrodes change into:

Vlca=Vs−Vd+2×K×Vad

Vlcb=Vs−Vd−2×K×Vad

respectively, where K=CCS/(CLC(V)+CCS).

Next, at a time T4, Vcsa falls from Vcom+Vad to Vcom−Vad and Vcsb rises from Vcom−Vad to Vcom+Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change from

Vlca=Vs−Vd+2×K×Vad

Vlcb=Vs−Vd−2×K×Vad

into

Vlca=Vs−Vd

Vlcb=Vs−Vd

respectively.

Next, at a time T5, Vcsa rises from Vcom−Vad to Vcom+Vad and Vcsb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change from

Vlca=Vs−Vd

Vlcb=Vs−Vd

into

Vlca=Vs−Vd+2×K×Vad

Vlcb=Vs−Vd−2×K×Vad

respectively.

After that, every time a period of time that is an integral number of times as long as one horizontal write period (or one horizontal scanning period) 1H has passed, the voltages Vcsa, Vcsb, Vlca and Vlcb alternate their levels at the times T4 and T5. The alternation interval between T4 and T5 may be appropriately determined to be one, two, three or more times as long as 1H according to the driving method of the liquid crystal display device (such as the polarity inversion method) or the display state (such as the degree of flicker or non-smoothness of the image displayed). This alternation is continued until the pixel 10 is rewritten next time, i.e., until the current time becomes equivalent to T1. Consequently, the effective values of the voltages Vlca and Vlcb applied to the subpixel electrodes become:

Vlca=Vs−Vd+K×Vad

Vlcb=Vs−Vd−K×Vad

respectively.

Therefore, the effective voltages V1 and V2 applied to the respective liquid crystal layers of the subpixels 10 a and 10 b become:

V1=Vlca−Vcom

V2=Vlcb−Vcom

That is to say,

V1=Vs−Vd+K×Vad−Vcom

V2=Vs−Vd−K×Vad−Vcom

respectively.

As a result, the difference ΔV12 (=V1−V2) between the effective voltages applied to the respective liquid crystal layers of the subpixels 10 a and 10 b becomes ΔV12=2×Kc×Vad (where K=CCS/(CLC(V)+CCS)). Thus, mutually different voltages can be applied to the liquid crystal layers.

FIG. 7 schematically shows the relation between V1 and V2. As can be seen from FIG. 7, the smaller the V1 value, the bigger ΔV12 in the liquid crystal display device 100A. Consequently, the γ characteristic at low grayscales (i.e., grayscales that are closer to black rather than to white) can be improved highly effectively.

Generally speaking, in a liquid crystal display device, the voltage applied to the liquid crystal layer of a pixel is set to be an AC voltage (such a method is sometimes called an “AC driving method”) to cope with a reliability problem. That is to say, the applied voltage is defined so that a pixel electrode and a counter electrode invert their potential levels at regular time intervals and that the electric field applied to the liquid crystal layer inverts its direction (i.e., the direction of electric lines of force) at regular time intervals. In a typical liquid crystal display device in which the counter electrode and pixel electrodes are arranged on two different substrates, the electric field applied to the liquid crystal layer inverts its direction from toward the light source to toward the viewer, and vice versa.

The interval at which the electric field applied to the liquid crystal layer inverts its direction is typically twice as long as one vertical scanning period. That is to say, in a liquid crystal display device, every time a picture is presented, the electric field applied to the liquid crystal layer inverts its direction. For that reason, in presenting a still picture, unless the electric field intensities (or applied voltages) exactly match with each other between the two electric field directions (i.e., if the electric field changes its intensity every time it changes its direction), the luminance of each pixel will change with such a variation in electric field intensity, thus producing a flicker on the screen.

In other words, to minimize such a flicker, the electric field intensities (or applied voltages) in those two electric field directions need to exactly match with each other. In liquid crystal display devices to be mass-produced on an industrial basis, however, it is difficult to exactly match the electric field intensities in those two directions. That is why they try to minimize the flicker by arranging pixels that have mutually opposite electric field directions adjacent to each other within a display area because the luminances of the pixels would be spatially averaged in that case. Such a method is generally called either a “dot inversion drive” or a “line inversion drive”. It should be noted that these “inversion drive” methods include not just the “one dot inversion” in which the polarities are inverted on a pixel-by-pixel basis in a “checkerboard pattern” so to speak (i.e., every row AND every column) and the “one line inversion” in which the polarities are inverted on a line-by-line basis but also a “two-row, one-column dot inversion” in which the polarities are inverted every other row and every column, and various other patterns. Thus, any of those various methods is appropriately adopted as needed.

FIG. 8 shows the display state to be produced when the liquid crystal display device disclosed in Patent Document No. 3 is driven by the one dot inversion drive method. Also, the waveforms of respective voltages (or signals) to realize the display state shown in FIG. 8 are shown in portions (a) through (j) of FIG. 9.

In the example to be described below, a plurality of pixels are arranged in columns (1 to cq) and rows (1 to rp) so as to form a matrix pattern (rp, cq), and each pixel P(p, q) (where and 1≦p≦rp and 1≦q≦cq) has two subpixels SPa(p, q) and SPb(p, q). FIG. 8 schematically illustrates a part of the relative arrangement (8 rows×6 columns) of source bus lines S-C1, S-C2, S-C3, S-C4, . . . and S-Ccq; gate bus lines G-L1, G-L2, G-L3, . . . and G-Lrp; CS bus lines CS-A and CS-B; pixels P(p, q); and subpixels SPa(p, q) and SPb(p, q) of the respective pixels.

As shown in FIG. 8, each pixel P(p, q) has subpixels SPa(p, q) and SPb(p, q) over and under its associated gate bus line G-Lp that extends horizontally approximately through the center of the pixel. That is to say, the subpixels SPa(p, q) and SPb(p, q) of each pixel are arranged in the column direction. In each of the subpixels SPa(p, q) and SPb(p, q), one of the two storage capacitor electrodes (not shown) thereof is connected to an adjacent CS bus line CS-A or CS-B. Also, a source bus line S-Cq to supply a signal voltage representing an image to be presented to the pixels P(p, q) runs vertically (in the column direction) between those pixels to supply the signal voltage to the TFTs (not shown) of the subpixels (or pixels) on the right-hand side of that source bus line. In the arrangement shown in FIG. 8, one CS bus line or one gate bus line are shared by two subpixels, thus achieving the effect of increasing the aperture ratio of the pixels.

By driving a liquid crystal display device with the configuration shown in FIG. 8 with voltages that have the voltage waveforms shown in portions (a) through (j) of FIG. 9, the one dot inversion drive can be carried out. In the following description, every pixel is supposed to be displaying a certain grayscale for the sake of simplicity.

Specifically, portion (a) of FIG. 9 shows the waveform of a display signal voltage (i.e., the waveform of a source signal voltage) to be supplied to the source bus lines S-C1, S-C3, S-C5, . . . and so on (such a group of odd-numbered source bus lines will be sometimes identified herein by SO). Portion (b) of FIG. 9 shows the waveform of a display signal voltage to be supplied to the source bus lines S-C2, S-C4, S-C6, . . . and so on (such a group of even-numbered source bus lines will be sometimes identified herein by SE). Portion (c) of FIG. 9 shows the waveform of a storage capacitor counter voltage supplied to a CS bus line CS-A and portion (d) of FIG. 9 shows the waveform of a storage capacitor counter voltage supplied to CS-B. And portions (e), (f), (g), (h), (i) and (j) of FIG. 9 show the waveforms of gate signal voltages supplied to gate bus lines G-L1, G-L2, G-L3, G-L4, G-L5, and G-L6, respectively. A period between a point in time when a voltage on one gate bus line changes from low level VgL into high level VgH and a point in time when a voltage on the next gate bus line changes from VgL into VgH is one horizontal scanning period (1H). Also, a period in which a voltage on a gate bus line keeps a high level (VgH) will be sometimes referred to herein as a “selected period PS”.

Since every pixel is supposed to be displaying a certain grayscale in this example, the display signal voltages (source signal voltages) shown in portions (a) and (b) of FIG. 9 have an oscillating waveform, of which the amplitude is always constant. One period of oscillation of the display signal voltage is two horizontal scanning periods (2H) and the polarity of the display signal voltage inverts every row. Also, the voltage waveforms of the source bus line SO (which may be S-C1, S-C3, and so on) and the source bus line SE (which may be S-C2, S-C4, and so on) have phases that are different from each other by 180 degrees, and the display signal voltage inverts its polarity every column. As a result, the one dot inversion drive can be carried out.

In general, in driving a TFT, when a voltage on a source bus line is applied to a subpixel electrode via the TFT, that voltage will slightly vary due to a variation in the waveform of the gate signal voltage. Such a phenomenon is sometimes called a “feedthrough phenomenon”. Thus, in view of such a feedthrough phenomenon, the counter voltage is set to be approximately a center value of the voltage waveform after the voltage on the source bus line has been applied to the subpixel electrode. In portions (a) and (b) of FIG. 9, a signal voltage corresponding to the waveform of a voltage that is applied to a subpixel electrode as a voltage that is higher than the counter voltage is identified by the sign “+”, while a signal voltage corresponding to the waveform of a voltage that is applied to a pixel electrode as a voltage that is lower than the counter voltage is identified by the sign “−”. These signs “+” and “−” correspond to the directions of the electric field applied to the liquid crystal layer. That is to say, the direction of the electric field applied to the liquid crystal layer when the sign is “+” is opposite to that of the electric field applied to it when the sign is “−”.

When a gate signal voltage on one gate bus line is VgH, a TFT connected to that gate bus line turns ON and the subpixel connected to that TFT is supplied with its display signal voltage. Next, after the voltage on that gate bus line gone VgL, the storage capacitor counter voltage changes. And as that storage capacitor counter voltage changes differently in terms of the magnitude, direction and sign of the variation with respect to two subpixels, the effective voltages applied to the respective liquid crystal layers of those subpixels become different from each other.

As shown in portion (c) and (d) of FIG. 9, in this example, the storage capacitor counter voltages on the CS bus lines CS-A and CS-B oscillate with the same amplitude and in the same period. For example, their amplitude may be twice as large as Vad (see FIG. 6) and their period may be 1 H. And if the phase of the oscillating waveform of one of CS-A and CS-B is shifted by 180 degrees, then that phase will match with that of the other's oscillating waveform. That is to say, their phases have a shift of 0.5H. If the first variation in voltage on a CS bus line associated with a given subpixel electrode is increase after the voltage on its associated gate bus line has changed from VgH into VgL, the average voltage applied to that subpixel electrode becomes higher than the display signal voltage on its associated source bus line when the voltage on its associated gate bus line is VgH. On the other hand, if the first variation in voltage on its associated CS bus line is decrease, the average voltage applied to that subpixel electrode becomes lower than the display signal voltage on its associated source bus line when the voltage on its associated gate bus line is VgH.

As a result, if the sign attached to the display signal voltage shown in portion (a) and (b) of FIG. 9 is “+” and if the variation in voltage on a CS bus line is increase, the effective voltage applied to the liquid crystal layer becomes higher than when the voltage variation is decrease. On the other hand, if the sign attached to the display signal voltage shown in portion (a) and (b) of FIG. 9 is “−” and if the variation in voltage on a CS bus line is increase, the effective voltage applied to the liquid crystal layer becomes lower than when the voltage variation is decrease.

FIG. 8 shows the states of each pixel P(p, q) and its subpixels SPa(p, q) and SPb(p, q) in one vertical scanning period (which will be referred to herein as a “frame period”). The following three signs that are arranged symmetrically with respect to a gate bus line associated with each pair of subpixels indicate the states of those subpixels.

The first sign “H” or “L” indicates which of the two effective voltages applied to those two subpixels is higher or lower than the other. That is to say, the sign “H” indicates that the effective voltage applied is relatively high and the sign “L” indicates that the effective voltage applied is relatively low. The second sign “+” or “−” indicates which of the two voltages applied to the counter electrode and the subpixel electrode is higher than the other (i.e., the direction of the electric field applied to the liquid crystal layer of that subpixel). That is to say, the sign “+” indicates that the voltage applied to the subpixel electrode is higher than the one applied to the counter electrode and the sign “−” indicates that the voltage applied to the subpixel electrode is lower than the one applied to the counter electrode. And the third sign “A” or indicates whether the given CS bus line is CS-A or CS-B.

For example, check out the states of the subpixels SPa(1, 1) and SPb(1, 1) of the pixel P(1, 1). As can be seen from portions (a) and (e) of FIG. 9, in the period in which GL-1 is selected (i.e., the period PS in which the voltage on that gate bus line is VgH), the display signal voltage is “+”. Also, when the gate signal voltage on GL-1 changes from VgH into VgL, the voltages on two CS bus lines associated with the two subpixels are in the states as indicated by the arrows (i.e., the leftmost set of arrows) shown in portion (c) and (d) of FIG. 9. Thus, the first variation in the storage capacitor counter voltage applied to SPa(1, 1) after the gate signal voltage on GL-1 has changed from VgH into VgL is “increase” (which is indicated by “U”) as can be seen from portion (c) of FIG. 9. On the other hand, the first variation in the storage capacitor counter voltage applied to SPb(1, 1) after the gate signal voltage on GL-1 has changed from VgH into VgL is “decrease” (which is indicated by “D”) as can be seen from portion (d) of FIG. 9. Consequently, the effective voltage applied to SPa(1, 1) increases but the one applied to SPb(1, 1) decreases. As a result, the effective voltage applied to SPa(1, 1) becomes higher than the one applied to SPb(1, 1), and therefore, the signs “H” and “L” are attached to SPa(1, 1) and SPb(1, 1), respectively.

As for the subpixels SPa(1, 2) and SPb(1, 2) of the pixel P(1, 2), in the period in which GL-1 is selected, the display signal voltage is “−” as can be seen from portion (b) of FIG. 9. Also, when the gate signal voltage on GL-1 changes from VgH into VgL, the voltages on two CS bus lines associated with the two subpixels are in the states as indicated by the arrows (i.e., the leftmost set of arrows) shown in portion (c) and (d) of FIG. 9. Thus, the first variation in the storage capacitor counter voltage applied to SPa(1, 2) after the gate signal voltage on GL-1 has changed from VgH into VgL is “increase” (which is indicated by “U”) as can be seen from portion (c) of FIG. 9. On the other hand, the first variation in the storage capacitor counter voltage applied to SPb(1, 2) after the gate signal voltage on GL-1 has changed from VgH into VgL is “decrease” (which is indicated by “D”) as can be seen from portion (d) of FIG. 9. Consequently, the effective voltage applied to SPa(1, 2) decreases but the one applied to SPb(1, 2) increases. As a result, the effective voltage applied to SPa(1, 1) becomes lower than the one applied to SPb(1, 2), and therefore, the signs “L” and “H” are attached to SPa(1, 2) and SPb(1, 2), respectively.

Furthermore, as for the subpixels SPa(2, 1) and SPb(2, 1) of the pixel P(2, 1), in the period in which GL-2 is selected, the display signal voltage is “−” as can be seen from portion (a) of FIG. 9. Also, when the gate signal voltage on GL-2 changes from VgH into VgL, the voltages on two CS bus lines associated with the two subpixels are in the states as indicated by the arrows (i.e., the second leftmost set of arrows) shown in portion (c) and (d) of FIG. 9. Thus, the first variation in the storage capacitor counter voltage applied to SPa(2, 1) after the gate signal voltage on GL-1 has changed from VgH into VgL is “decrease” (which is indicated by “D”) as can be seen from portion (d) of FIG. 9. On the other hand, the first variation in the storage capacitor counter voltage applied to SPb(2, 1) after the gate signal voltage on GL-2 has changed from VgH into VgL is “increase” (which is indicated by “U”) as can be seen from portion (c) of FIG. 9. Consequently, the effective voltage applied to SPa(2, 1) increases but the one applied to SPb(2, 1) decreases. As a result, the effective voltage applied to SPa(2, 1) becomes higher than the one applied to SPb(1, 2), and therefore, the signs “H” and “L” are attached to SPa(2, 1) and SPb(2, 1), respectively. It can be seen that the respective subpixels come have the states shown in FIG. 8 in this manner.

Optionally, if the phase of the voltage waveform on each source bus line SO (shown in portion (a) of FIG. 9) or SE (shown in portion (b) of FIG. 9) is shifted by 180 degrees in the frame that follows the frame shown in FIG. 9, an AC drive in which the direction of the electric field applied to the liquid crystal layer inverts every frame period can be carried out.

Furthermore, to prevent the order of the magnitudes of the effective voltages applied to the respective subpixels of each pixel (i.e., the arrangement of the respective orders of the magnitudes of those subpixels' luminances within the display screen as indicated by the arrangement pattern of the signs “H” and “L” in FIG. 8) from changing every frame, whenever the phase of the voltage waveform on a source bus line is shifted, the phase of the voltage waveforms on the CS bus lines CS-A and CS-B may also be shifted by 180 degrees. Then, in the frame that follows the one shown in FIG. 8, each set of the signs “+” and “−” shown in FIG. 8 can be exchanged with each other (e.g., (+, H)

(−, H) and (+, L)

(−, L)).

As shown in FIG. 8, the signs “+” and “−” indicating the polarities (i.e., the directions of the electric field) of the respective pixels invert in a period of two pixels (i.e., two columns) both in the row direction (i.e., horizontally) and in the column direction (i.e., vertically) in the order of (+, −), (+, −), (+, −), (+, −), and so on. That is to say, one dot inversion is realized when viewed on a pixel basis.

Next, subpixels of a high luminance rank (i.e., bright subpixels identified by the sign “H” in FIG. 8) will be considered. As for the row direction (e.g., as for SPa on the first row), their polarities do not invert and remain +H, +H, +H and so on. In the column direction (e.g., as for the first column, for example), on the other hand, their polarities invert in a period of two pixels (i.e., two rows) in the order of (+H, −H), (+H, −H), (+H, −H), (+H, −H), and so on. That is to say, the line inversion drive is realized as for such subpixels of a high luminance rank. Dark subpixels identified by the sign “L” are also arranged in a similar regular pattern.

As shown in FIG. 8, if the one dot inversion drive is carried out by the multi-pixel driving method disclosed in Patent Document No. 3, then bright subpixels will be arranged in the checkerboard pattern. For example, look at a row of pixel, and it can be seen that bright subpixels are arranged in a zigzag pattern in the row direction in accordance with the arrangement of the polarities of the display signal voltages applied to the respective liquid crystal layers of the pixels. That is to say, if the bright subpixel is located in the upper half of a pixel when viewed in the column direction, then the bright subpixel will be located in the lower half of another pixel, which is adjacent to the former in the row direction, when viewed in the column direction. Consequently, when lines that are parallel to each other in the row direction are displayed, those lines will look smeared, which is a problem.

Next, it will be described with reference to FIGS. 3 through 5 how the liquid crystal display device 100A as an embodiment of the present invention can overcome the problem described above.

FIG. 3 shows the waveforms of various voltages (or signals) to drive the liquid crystal display device 100A as an embodiment of the present invention. In FIG. 3, shown are gate signal voltages Vg(m) through Vg(m+7), CS signal voltages Vcsa and Vcsb, and voltages Vlca(m) through Vlca(m+7) and Vlcb(m) to be applied to the respective liquid crystal layers of subpixels. Specifically, Vlca(m) through Vlca(m+7) represent the waveforms of the voltages applied to the respective liquid crystal layers of bright subpixels. On the other hand, since the voltages applied to the respective liquid crystal layers of dark subpixels have the same waveform in any row of pixels, only Vlcb(m) is shown in FIG. 3. It should be noted that if display signal voltages with the waveforms shown in portions (a) and (b) of FIG. 9 are used as the display signal voltages to be supplied to source bus lines, the one dot inversion drive can be carried out.

As shown in FIG. 3, the voltage waveform of the oscillation voltage Vcsa applied to the CS bus line 24 a (associated with bright subpixels) of the liquid crystal display device 100A has at least three potentials, which include two potentials that define the maximum amplitude Vcsa(p-p) of the oscillation voltage (corresponding to 2Vadd), and one potential that agrees with the average potential of the oscillation voltage. In this case, the “average potential of the oscillation voltage” does not always refer to a simple average of the two potentials that define the maximum amplitude of the oscillation voltage but to an “effective average” of the oscillation voltage. More specifically, in one period of the oscillation voltage waveform, the sum of the areas of portions that are higher than the average potential becomes equal to that of the area of portions that are lower than it. It should be noted that the oscillation voltage to be described below has a waveform that is symmetric with respect to the centerline between two potentials that define the maximum amplitude, the simple average of those two potentials that define the maximum amplitude of the oscillation voltage agrees with the effective average of the oscillation voltage.

Also, in a period of time in which the oscillation voltage has a potential that is equal to the average potential of the oscillation voltage waveform (i.e., in the flat portion), TFTs, belonging to the pixels that are connected to the CS bus line to which that oscillation voltage is applied, are turned OFF. In the following example, the instant the gate bus line voltage decreases to VgL to turn OFF the TFTs is in the middle of the period in which the oscillation voltage has the average potential. In this example, the oscillation voltage waveform has the three potentials described above. However, the oscillation voltage waveform may also have more than three potentials (e.g., five, seven or nine potentials) as well as long as those three potential are included.

The effective voltage V1 applied to the respective liquid crystal layers of the bright subpixels is obtained by calculating the integral of the squared amplitudes of the hatched portions of Vlca(m) shown in FIG. 3 with time and then calculating its average with time. In this case, the effective voltages are obtained for one vertical scanning period. On the other hand, the effective voltage V2 applied to the respective liquid crystal layers of the dark subpixels is obtained by calculating the integral of the squared amplitudes of the hatched portions of Vlcb(m) shown in FIG. 3 and then calculating its squared average. Consequently, since the oscillation voltage is superposed on the display signal voltage, the effective voltage V1 is always greater than the effective voltage V2 irrespective of the polarity of the display oscillation voltage. Also, by making settings so that the moment when the gate bus line voltage becomes VgL to turn the TFTs OFF falls within, and is located just at the middle of, a period in which the oscillation voltage has an average potential, it is possible to prevent the average of the voltages applied to the respective liquid crystal layers of the bright subpixels from varying under the influence of the oscillation voltage. In this respect, the entire disclosure of Japanese Laid-Open Patent Publication No. 2005-99746 is hereby incorporated by reference.

As described above, it would be best to set the moment when the TFTs are turned OFF at just the middle of the period in which the oscillation voltage has the average potential. However, as long as the moment when the TFTs are turned OFF falls within the period in which the oscillation voltage has the average potential, the average of the voltages applied to the respective liquid crystal layers can be substantially constant. Also, it is beneficial if the potential of the oscillation voltage when the TFTs are turned OFF is the average of the oscillation voltage as described above. However, as long as that potential is between the two potentials that define the maximum amplitude, the display states shown in FIGS. 5A and 5B are realized to say the least.

FIG. 4 is a graph showing how the effective voltages V1 and V2 applied to the respective liquid crystal layers of subpixels change with the display signal voltage Vs when an oscillation voltage with an amplitude 2Vadd is applied. In this case, the value of 2Vadd is set so that when the display signal voltage is 0 volts, the V1 value becomes equal to 2 V. The greater the 2Vadd value, the larger the V1 value, too.

The larger the display signal voltage value, the closer to the display signal voltage value the V1 value gets. On the other hand, the V2 value is always equal to the display signal voltage value. Thus, it can be seen that in this liquid crystal display device 100A, V1 and V2 also satisfy the relation shown in FIG. 7 as in the liquid crystal display device of Patent Document No. 3, and the viewing angle dependence of the γ characteristic can also be reduced no less effectively.

FIG. 5A schematically illustrates a display state when the liquid crystal display device 100A is driven by the one-dot inversion drive method. FIG. 5A corresponds to FIG. 8 that has already been referred to, and uses the same signs as what is used in FIG. 8.

As can be seen from FIG. 5A, in this liquid crystal display device 100A, subpixels SPa associated with each CS bus line CS-A, to which an oscillation voltage Vcsa is supplied, become bright subpixels irrespective of the polarity of the display signal voltage. Thus, look at a row of pixels, and it can be seen that those pixels are arranged so that their respective bright subpixels are located at the same position in the column direction and arranged in line. For example, on the first row, the bright subpixels are arranged in the upper half of every pixel in the column direction. On the second row, on the other hand, the bright subpixels are arranged in the lower half of every pixel in the column direction. Next, on the third row, the bright subpixels are arranged in the upper half of every pixel in the column direction. And on the fourth row, the bright subpixels are arranged in the lower half of every pixel in the column direction. In this manner, the respective bright subpixels of a column of pixels alternately change their positions vertically in the column direction because a configuration in which a single CS bus line is shared by a plurality of pixels that are adjacent to each other in the column direction is adopted in this embodiment. If two CS bus lines are provided for each pixel, however, the bright subpixels can be arranged in the upper half of every pixel in the column direction (see FIG. 5B).

As shown in FIG. 5A, the signs “+” and “−” indicating the polarities (i.e., the directions of the electric field) of the respective pixels invert in a period of two pixels (i.e., two columns) both in the row direction (i.e., horizontally) and in the column direction (i.e., vertically) in the order of (+, −), (+, −), (+, −), (+, −), and so on. That is to say, one dot inversion is realized when viewed on a pixel basis.

Next, subpixels of a high luminance rank (i.e., subpixels identified by the sign “H” in FIG. 5A) will be considered. As for the row direction (e.g., as for SPa on the first row), their polarities invert in a period of two pixels (i.e., two rows) in the order of (+H, −H), (+H, −H), (+H, −H), and so on. In the column direction (e.g., as for the first column, for example), on the other hand, their polarities invert in a period of two pixels (i.e., two rows) in the order of (+H, −H), (+H, −H), (+H, −H), (+H, −H), and so on. That is to say, the one-dot inversion drive is also realized as for such subpixels of a high luminance rank. Subpixels identified by the sign “L” are also arranged in a similar regular pattern.

Thus, it can be seen that in this liquid crystal display device 100A, the polarities of the voltages applied to the respective liquid crystal layers are distributed on a smaller unit, and flicker is much less likely to occur, than in the liquid crystal display device of Patent Document No. 3 shown in FIG. 8.

Even in the liquid crystal display device 100B shown in FIG. 2( b), a row of pixels can also be arranged so that their respective bright subpixels are located at the same position in the column direction and arranged in line as in the liquid crystal display device 100A. FIG. 5B schematically illustrates how the liquid crystal display device 100B performs a display operation when driven by the one-dot inversion drive using the same signal voltages as what has already been described for the liquid crystal display device 100A. It should be noted that the liquid crystal display device 100B does not have the storage capacitors 22 b of the liquid crystal display device 100A, and therefore, does not need the CS signal voltage Vcb.

Comparing FIG. 5B to FIG. 5A, it can be seen easily that the bright subpixel of every pixel on a row is located at the same position in the column direction (i.e., in the upper position in this example) in FIG. 5B, which is a difference from the arrangement shown in FIG. 5A. In this liquid crystal display device 100B, the one-dot inversion drive can also be carried out not only on a pixel-by-pixel basis but also on a bright subpixel basis as well. On top of that, in this liquid crystal display device 100B, the bright subpixel of every pixel on a row is located at the same position in the column direction. That is to say, two pixels that are adjacent to each other in the row direction have their bright and dark subpixels arranged in the same pattern, so do two pixels that are adjacent to each other in the column direction. In other words, in this liquid crystal display device 100B, bright subpixels are never adjacent to each other in the column direction. Consequently, it can be said that the display state shown in FIG. 5B achieves a higher spatial resolution than the display state shown in FIG. 5A. It should be noted that if the storage capacitors 22 b of the dark subpixels could not be omitted, the display state shown in FIG. 5B could be achieved by providing two CS bus lines for each pixel in the liquid crystal display device 100A as described above.

In the liquid crystal display devices 100A and 100B according to embodiments of the present invention, by determining, irrespective of the polarity of the display signal voltage, what subpixels the oscillation voltage needs to be applied to, subpixels to be the bright subpixels can be selected. This will be advantageous when applied to a liquid crystal display device, of which each row of pixels is comprised of pixels representing an even number of colors.

In a known general liquid crystal display device, three pixels representing the colors red, green and blue that are the three primary colors of light form one color display pixel. And by controlling the luminances of those pixels, the known liquid crystal display device conducts a color display operation. It should be noted that the “color display pixel” and “pixels” used here in this description are sometimes called a “pixel” and “subpixels” elsewhere. As for the arrangement of pixels (or the arrangement of color filters), a striped arrangement is ordinarily used. If such a liquid crystal display device, of which one color display pixel is comprised of R, G and B pixel that are arranged in the row direction, is driven by the one-dot inversion drive method, then a row of pixels will have a polarity pattern such as R(+), G(−), B(+), R(−), G(+), B(−) and so on. That is to say, if the polarity of the voltage applied to an adjacent pixel is inverted, then the polarity of the voltage applied to the next pixel representing the same color also inverts.

Meanwhile, in a liquid crystal display device that has been developed recently to have an expanded color reproduction range, one color display pixel is comprised of not only red (R), green (G) and blue (B) pixels but also a yellow (Y), cyan (C) or magenta (M) pixel as well. If such a liquid crystal display device in which four pixels representing those colors are periodically arranged in the same order in the row direction is driven by the one-dot inversion drive, then a row of pixels will have a polarity pattern such as R(+), G(−), B(+), Y(−), R(+), G(−), B(+), Y(−) and so on and a voltage of the same polarity will be applied to pixels in the same color. Therefore, in the liquid crystal display device of Patent Document No. 3 shown in FIG. 8, if the first, second, third and fourth columns are supposed to be R, G, B and Y (which will be arranged in the same order after that), then the respective bright subpixels of the R and B pixels will be located in the upper half thereof in the column direction. Then, parallel lines that are displayed in the row direction will look not only smeared but also spotted as well, which is also a problem. For example, when gray lines are displayed, R and B pixels, of which the bright subpixels are located in the upper half, will look spotted. It should be noted that if a white pixel is added instead of the Y pixel, then the color reproduction range cannot be expanded but the display luminance can be increased. Nevertheless, the same problem as what has just been described will arise in that case, too.

In the liquid crystal display device 100A, 100B, on the other hand, the bright subpixels of pixels in all colors are arranged straight in line in the row direction. That is why even when such parallel lines are displayed in the row direction, it is possible to prevent those lines running in the row direction from looking spotted.

In the example described above, the oscillation voltage Vcsa is supposed to be have a period of oscillation of 2H. However, one period of oscillation may also be 1H. But if one period of the oscillation voltage is short, then its waveform will get blunted due to a CR time constant of the CS bus line (i.e., an approximated value of the load impedance of the CS bus line). To avoid such a situation, one period of oscillation of the oscillation voltage had better be at least eight times as long as the CR time constant of the CS bus line. In that case, however, the phases of the respective oscillation voltages need to be adjusted for each row of pixels so that the moment when the TFT turns OFF falls within a period in which the oscillation voltage has the third potential. For that purpose, N electrically independent CS trunk lines may be provided and be supplied with mutually different oscillation voltages. Then, the oscillation voltage can have an extended period with the condition described above satisfied. In terms of its idea about the relation between one period of the oscillation voltage and the number of electrically independent CS trunk lines, the entire disclosure of Japanese Patent Publication No. 4104639 is hereby incorporated by reference.

The multi-pixel drive does not have to be carried out in every grayscale but may be applied to only required ones. For example, if a display operation is conducted in 256 grayscales of #0 through #255, the multi-pixel drive could be turned ON only when the display operation is conducted in low grayscales (e.g., in either Grayscale #96 or less or Grayscale #64 or less). Since the γ characteristic of a normally black mode liquid crystal display device exhibits significant viewing angle dependence in such low grayscales, the viewing angle dependence of the γ characteristic can also be reduced even when such a driving method is adopted.

In the foregoing description, the row direction is supposed to be the horizontal direction on the display screen and the column direction is supposed to be the vertical direction there. However, these two directions may also be switched. That is to say, the gate bus lines may also be arranged to run vertically and the source bus lines may also be arranged to run horizontally. In other words, the row and column directions described above may be changed with each other. Also, in the foregoing description, the CS bus lines are supposed to run parallel to the gate bus lines. But the CS bus lines may also run parallel to the source bus lines.

INDUSTRIAL APPLICABILITY

The present invention is broadly applicable to not only an MVA mode liquid crystal display device but also PSA (polymer sustained alignment) mode, RTN mode (also called “VATN mode”), IPS mode and FSS mode liquid crystal display devices as well.

REFERENCE SIGNS LIST

-   10 pixel -   10 a, 10 b subpixel -   12 gate bus line -   13 a, 13 b liquid crystal capacitor -   14 source bus line -   16 a, 16 b TFT -   18 a, 18 b subpixel electrode -   22 a, 22 b storage capacitor -   24 a, 24 b CS bus line -   100A, 100B liquid crystal display device 

1. A liquid crystal display device comprising: a plurality of pixels that are arranged in columns and rows to form a matrix pattern, each of the plurality of pixels including first and second subpixels, the first subpixel exhibiting a higher luminance than the second subpixel at least at a particular grayscale; a plurality of source bus lines, each of which is associated with one of the columns of pixels; a plurality of gate bus lines, each of which is associated with one of the rows of pixels; a plurality of TFTs, each of which is associated with one of the first and second subpixels that each said pixel has; and a plurality of first CS bus lines, each of which is associated with the first subpixel of one of the pixels, wherein the first subpixel includes: a liquid crystal capacitor which is formed by a first subpixel electrode, a liquid crystal layer, and a counter electrode that faces the first subpixel electrode via the liquid crystal layer; and a first storage capacitor which is formed by a first storage capacitor electrode that is electrically connected to the first subpixel electrode, an insulating layer, and a first storage capacitor counter electrode that faces the first storage capacitor electrode via the insulating layer, and wherein the second subpixel includes a liquid crystal capacitor that is formed by a second subpixel electrode and a counter electrode that faces the second subpixel electrode via the liquid crystal layer, and wherein a first CS signal voltage that is applied to the first storage capacitor counter electrode through its associated first CS bus line is an oscillation voltage, of which one period is shorter than one vertical scanning period, and has at least three potentials including first and second potentials that define a maximum amplitude and a third potential between the first and second potentials, and wherein when a gate signal voltage that is supplied to the gate bus line associated with an arbitrary row of pixels and that has been high goes low, the first CS signal voltage supplied to its associated first CS bus line is at the third potential.
 2. The liquid crystal display device of claim 1, wherein the third potential is the average of the first and second potentials.
 3. The liquid crystal display device of claim 1, further comprising a plurality of second CS bus lines, each of which is associated with the second subpixel of one of the pixels, wherein the second subpixel includes a second storage capacitor which is formed by a second storage capacitor electrode that is electrically connected to the second subpixel electrode, an insulating layer, and a second storage capacitor counter electrode that faces the second storage capacitor electrode via the insulating layer, and wherein a second CS signal voltage applied to the second storage capacitor counter electrode through its associated second CS bus line is constant through one vertical scanning period.
 4. The liquid crystal display device of claim 3, wherein the second CS signal voltage is equal to a counter voltage applied to the counter electrode.
 5. The liquid crystal display device of claim 1, wherein the second subpixel has no storage capacitors.
 6. The liquid crystal display device of claim 1, wherein the first and second subpixels are arranged in the same pattern both in two pixels that are adjacent to each other in a row direction and in two pixels that are adjacent to each other in a column direction.
 7. The liquid crystal display device of claim 1, wherein each of the plurality of first CS bus lines is connected to one of N CS trunk lines that are electrically independent of each other. 